8a096a09e4
Remove extra register use in sign extension instructions
2019-11-18 11:47:58 -08:00
344132cc89
Merge branch 'master' into feature/singlepass-sign-extension
2019-11-18 11:38:12 -08:00
8b6a7b77fc
Clean up from feedback
2019-11-18 11:36:49 -08:00
7631aee4f4
Add sign extension spec tests; add sign extension to singlepass
2019-11-15 21:54:34 -08:00
3b2d751c55
Enable compilation for specific target
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By exposing the target information through `CompilerConfig`,
compiler(only LLVM at the moment) could create a machine with
different CPU feature flags other than current host, which makes it
capable to "cross compile" to some degree.
Update #959
2019-11-15 18:51:59 -08:00
11f34a9285
feat(clif-backend,singlepass-backend) Feed imported functions with FuncCtx.vmctx.
2019-11-12 00:51:57 +01:00
a4ba429ed0
feat(singlepass-backend) Inject FuncCtx to the function pointer of an host function.
2019-11-06 14:48:46 +01:00
edb6cbefca
fix(runtime-core) Share the definition of Trampoline across all the backends.
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This patch updates all the backends to use the definition of
`Trampoline` as defined in the `wasmer_runtime_core::typed_func`
module. That way, there is no copy of that type, and as such, it is
easier to avoid regression (a simple `cargo check` does the job).
This patch also formats the `use` statements in the updated files.
2019-10-30 13:10:34 +01:00
77527c23ce
Merge #877
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877: Reimplement F32Min, F32Max, F64Min and F64Max. r=nlewycky a=nlewycky
# Description
Reimplement F32Min, F32Max, F64Min and F64Max.
Adds XMM8--15 registers. Adds VMOVA, VBLEND and VXORP, and the VCMPUNORD and VCMPORD comparisons.
Fixes 419 test failures.
Co-authored-by: Nick Lewycky <nick@wasmer.io >
2019-10-22 17:33:44 +00:00
e559b54309
fix(singlepass-backend) Use wasmparser from runtime-core.
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The `wasmer-runtime-core` crate re-exports the `wasmparser`
crate. This patch updates the `singlepass-backend` crate to use
`wasmparser` through the `wasmer-runtime-core` crate, which removes a
direct dependency for this crate.
2019-10-18 11:22:40 +02:00
99f7499a05
Reimplement I32Ctz, I64Clz and I64Ctz without LZCNT or TZCNT.
2019-10-15 13:42:05 -07:00
cafcfd3b50
cargo fmt
2019-10-15 13:07:44 -07:00
cf3d2a830d
Reimplement I32Clz without relying on LZCNT.
2019-10-15 12:50:59 -07:00
26a4f073f0
Implement F64Min and F64Max.
2019-10-14 14:15:18 -07:00
06ffb00deb
Reimplement F32Max.
2019-10-14 14:07:30 -07:00
b886a41a85
Use temp_gprs instead of hard-coding RAX/RDX.
2019-10-14 13:53:30 -07:00
5cee23455d
Release the registers we acquire. Reformat.
2019-10-14 13:51:03 -07:00
336dab7fd9
Don't use utility functions in F32Min implementation.
2019-10-14 13:46:55 -07:00
4b89e01806
Remove commented-out code that I added so as to not lose its history in git. Apply trivial cleanups and reformat.
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Remove expected test failure entries that are fixed so far.
2019-10-14 13:46:55 -07:00
963148fdce
Fix F32Min for all cases including NaNs.
2019-10-14 13:46:55 -07:00
8b937afc1f
Add comments to indicate the implemention we'd like to have, but can't right now.
2019-10-14 13:46:55 -07:00
0f712c90ab
Don't allocate another register when it's safe to reuse dst.
2019-10-14 13:46:55 -07:00
b75e5c0c7c
When we know RDX is unavailable, use RAX instead. Should be fine here.
2019-10-14 13:46:55 -07:00
d6eba03a2f
Remove loc1/loc2. That intended refactoring didn't work out.
2019-10-14 13:46:55 -07:00
555d933057
Initial commit, reimplementation of F32Min. Fixes F32Min(negative_zero, zero) issue.
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Also removes some previously-fixed i32 and i64 exclusions from the tests.
2019-10-14 13:46:55 -07:00
ab76c2357f
Delete dead (commented out) code. NFC.
2019-10-02 16:31:11 -07:00
83b678bc36
Give this function a better name.
2019-10-02 16:31:11 -07:00
ba68cfc2c6
Finish atomic operations for singlepass, excluding wait and notify.
2019-10-02 16:31:11 -07:00
bc7e017188
Add atomic.rmw operations, excluding xchg and cmpxchg.
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Sizes are now ordered, to facilitate an assertion that one size is less (smaller) than another.
panic! error messages are provided for remaining emitter functions.
2019-10-02 16:31:11 -07:00
f021d59a0b
Refactor out a compare-and-swap loop function.
2019-10-02 16:31:11 -07:00
cd1d06f5a5
Initial working implementation of I32AtomicRmwAnd!
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Adds the ability to reserve a specific temp-gpr register. Needed for CMPXCHG which always uses RAX.
2019-10-02 16:31:11 -07:00
6937019b65
Use a compare-and-swap loop for AND.
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BUG: This might allocate RAX twice.
2019-10-02 16:31:10 -07:00
efc89e829d
Add i32 rmw add and sub.
2019-10-02 16:31:10 -07:00
98f35ef84a
Initial implementation of atomic load/store and i32 atomic rmw add.
2019-10-02 16:31:10 -07:00
be181f9119
Correct this test and simplify.
2019-09-24 10:54:23 -07:00
07b5991080
No need to emit add of constant zero.
2019-09-23 15:01:19 -07:00
00c2e09f43
fix CodeGen message type
2019-09-16 11:00:03 +02:00
33ba6768bc
replace panics by CodeGen Error in codegen_x64
2019-09-16 09:56:41 +02:00
d8471e2b6a
Improved docs with custom logo and favicon
2019-09-03 17:06:31 -07:00
bf9d915635
Fix a few issues from PR comments.
2019-08-21 14:53:33 -07:00
124ad73e8a
Merge remote-tracking branch 'origin/master' into feature/llvm-osr
2019-08-19 13:06:59 -07:00
afa0600701
Cargo fmt
2019-08-15 19:13:00 -07:00
6a24485999
Insert trampolines to preserve callee-saved registers for backends without register save area information.
2019-08-15 19:10:24 -07:00
98d3e04137
Fix unused mut warning
2019-08-15 20:09:51 -06:00
439e81d41e
Fix singlepass error when no function code present
2019-08-15 10:15:58 -06:00
98ef9182d7
Run clang-format and cargo fmt
2019-08-14 16:35:40 -07:00
0e0573c73c
Merge remote-tracking branch 'origin/master' into feature/llvm-osr
2019-08-14 16:33:26 -07:00
9cade2b441
singlepass: Skip patchpoint.
2019-08-10 03:10:32 +08:00
5a41686192
Fix bare_trait_objects warnings
2019-08-08 16:46:52 -06:00
c1619026d5
Swap code lazily when tiering up from singlepass to LLVM.
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Does not handle long-running functions, but should work at least.
2019-08-09 04:26:17 +08:00
