edb6cbefca
fix(runtime-core) Share the definition of Trampoline across all the backends.
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This patch updates all the backends to use the definition of
`Trampoline` as defined in the `wasmer_runtime_core::typed_func`
module. That way, there is no copy of that type, and as such, it is
easier to avoid regression (a simple `cargo check` does the job).
This patch also formats the `use` statements in the updated files.
2019-10-30 13:10:34 +01:00
82f258b888
Prepare for 0.9.0 release
2019-10-23 13:40:35 -07:00
77527c23ce
Merge #877
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877: Reimplement F32Min, F32Max, F64Min and F64Max. r=nlewycky a=nlewycky
# Description
Reimplement F32Min, F32Max, F64Min and F64Max.
Adds XMM8--15 registers. Adds VMOVA, VBLEND and VXORP, and the VCMPUNORD and VCMPORD comparisons.
Fixes 419 test failures.
Co-authored-by: Nick Lewycky <nick@wasmer.io >
2019-10-22 17:33:44 +00:00
e559b54309
fix(singlepass-backend) Use wasmparser from runtime-core.
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The `wasmer-runtime-core` crate re-exports the `wasmparser`
crate. This patch updates the `singlepass-backend` crate to use
`wasmparser` through the `wasmer-runtime-core` crate, which removes a
direct dependency for this crate.
2019-10-18 11:22:40 +02:00
cd0b49e661
popcnt for aarch64.
2019-10-18 00:18:15 +08:00
a057296618
(S32, Imm64, GPR)
2019-10-17 23:45:58 +08:00
3f35a74b84
Two more mov variants.
2019-10-17 23:40:44 +08:00
4df7973639
Add mov variants.
2019-10-17 23:34:24 +08:00
00242cdd7f
Fix LEA simulation on aarch64.
2019-10-17 23:00:50 +08:00
d325635629
Increment aarch64 virtual stack size to 1MB.
2019-10-17 23:00:32 +08:00
4e5d559ab5
Remove dead functions LZCNT and TZCNT.
2019-10-15 13:44:18 -07:00
99f7499a05
Reimplement I32Ctz, I64Clz and I64Ctz without LZCNT or TZCNT.
2019-10-15 13:42:05 -07:00
cafcfd3b50
cargo fmt
2019-10-15 13:07:44 -07:00
cf3d2a830d
Reimplement I32Clz without relying on LZCNT.
2019-10-15 12:50:59 -07:00
3de0c7763f
Skip inline non-instruction data.
2019-10-15 22:12:08 +08:00
81d538ade2
Fix disp < 0 case.
2019-10-15 22:00:33 +08:00
ee88c459e5
Allow arbitrary size of disp.
2019-10-15 21:55:04 +08:00
26a4f073f0
Implement F64Min and F64Max.
2019-10-14 14:15:18 -07:00
06ffb00deb
Reimplement F32Max.
2019-10-14 14:07:30 -07:00
b886a41a85
Use temp_gprs instead of hard-coding RAX/RDX.
2019-10-14 13:53:30 -07:00
5cee23455d
Release the registers we acquire. Reformat.
2019-10-14 13:51:03 -07:00
336dab7fd9
Don't use utility functions in F32Min implementation.
2019-10-14 13:46:55 -07:00
765e1d3b9e
Add XMM8--XMM15. These were added in x64.
2019-10-14 13:46:55 -07:00
4b89e01806
Remove commented-out code that I added so as to not lose its history in git. Apply trivial cleanups and reformat.
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Remove expected test failure entries that are fixed so far.
2019-10-14 13:46:55 -07:00
963148fdce
Fix F32Min for all cases including NaNs.
2019-10-14 13:46:55 -07:00
8b937afc1f
Add comments to indicate the implemention we'd like to have, but can't right now.
2019-10-14 13:46:55 -07:00
0f712c90ab
Don't allocate another register when it's safe to reuse dst.
2019-10-14 13:46:55 -07:00
b75e5c0c7c
When we know RDX is unavailable, use RAX instead. Should be fine here.
2019-10-14 13:46:55 -07:00
d6eba03a2f
Remove loc1/loc2. That intended refactoring didn't work out.
2019-10-14 13:46:55 -07:00
555d933057
Initial commit, reimplementation of F32Min. Fixes F32Min(negative_zero, zero) issue.
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Also removes some previously-fixed i32 and i64 exclusions from the tests.
2019-10-14 13:46:55 -07:00
a525907c60
Emit state information for internal breakpoints.
2019-10-14 20:23:10 +08:00
5499a69ddc
Run cargo fmt on everything.
2019-10-13 20:02:47 +08:00
36f95fc660
Support emitting inline breakpoints in singlepass.
2019-10-11 21:05:42 +08:00
8ee4b7f7b0
Replace brk with undefined instruction.
2019-10-10 22:08:52 +08:00
f63c706abc
Merge branch 'master' into feature/singlepass-atomicops
2019-10-02 16:46:59 -07:00
ab76c2357f
Delete dead (commented out) code. NFC.
2019-10-02 16:31:11 -07:00
8e63d54fdb
cargo fmt
2019-10-02 16:31:11 -07:00
83b678bc36
Give this function a better name.
2019-10-02 16:31:11 -07:00
11c5e0d71d
Make the panics a bit more descriptive.
2019-10-02 16:31:11 -07:00
ba68cfc2c6
Finish atomic operations for singlepass, excluding wait and notify.
2019-10-02 16:31:11 -07:00
bc7e017188
Add atomic.rmw operations, excluding xchg and cmpxchg.
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Sizes are now ordered, to facilitate an assertion that one size is less (smaller) than another.
panic! error messages are provided for remaining emitter functions.
2019-10-02 16:31:11 -07:00
f021d59a0b
Refactor out a compare-and-swap loop function.
2019-10-02 16:31:11 -07:00
cd1d06f5a5
Initial working implementation of I32AtomicRmwAnd!
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Adds the ability to reserve a specific temp-gpr register. Needed for CMPXCHG which always uses RAX.
2019-10-02 16:31:11 -07:00
6937019b65
Use a compare-and-swap loop for AND.
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BUG: This might allocate RAX twice.
2019-10-02 16:31:10 -07:00
81895830f0
Add emitter for LOCK CMPXCHG so that we can emit compare-and-swap loops.
2019-10-02 16:31:10 -07:00
efc89e829d
Add i32 rmw add and sub.
2019-10-02 16:31:10 -07:00
98f35ef84a
Initial implementation of atomic load/store and i32 atomic rmw add.
2019-10-02 16:31:10 -07:00
c77cbc1f40
Prepare for 0.8.0 release
2019-10-02 15:40:35 -07:00
9be72e6808
Fix some other files too
2019-09-30 22:50:04 -07:00
b304317682
More mov variants.
2019-09-30 01:01:15 +08:00
