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Remove extra register use in sign extension instructions

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This commit is contained in:
Mark McCaskey
2019-11-18 11:47:58 -08:00
parent 344132cc89
commit 8a096a09e4
1 changed files with 5 additions and 21 deletions
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26
lib/singlepass-backend/src/codegen_x64.rs
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@ -2964,18 +2964,15 @@ impl FunctionCodeGenerator<CodegenError> for X64FunctionCode {
)[0]; )[0];
self.value_stack.push(ret); self.value_stack.push(ret);
let tmpg1 = self.machine.acquire_temp_gpr().unwrap();
a.emit_mov(Size::S32, loc, Location::GPR(tmpg1));
Self::emit_relaxed_zx_sx( Self::emit_relaxed_zx_sx(
a, a,
&mut self.machine, &mut self.machine,
Assembler::emit_movsx, Assembler::emit_movsx,
Size::S8, Size::S8,
Location::GPR(tmpg1), loc,
Size::S32, Size::S32,
ret, ret,
); );
self.machine.release_temp_gpr(tmpg1);
} }
Operator::I32Extend16S => { Operator::I32Extend16S => {
let loc = let loc =
@ -2987,18 +2984,15 @@ impl FunctionCodeGenerator<CodegenError> for X64FunctionCode {
)[0]; )[0];
self.value_stack.push(ret); self.value_stack.push(ret);
let tmpg1 = self.machine.acquire_temp_gpr().unwrap();
a.emit_mov(Size::S32, loc, Location::GPR(tmpg1));
Self::emit_relaxed_zx_sx( Self::emit_relaxed_zx_sx(
a, a,
&mut self.machine, &mut self.machine,
Assembler::emit_movsx, Assembler::emit_movsx,
Size::S16, Size::S16,
Location::GPR(tmpg1), loc,
Size::S32, Size::S32,
ret, ret,
); );
self.machine.release_temp_gpr(tmpg1);
} }
Operator::I64Extend8S => { Operator::I64Extend8S => {
let loc = let loc =
@ -3010,19 +3004,15 @@ impl FunctionCodeGenerator<CodegenError> for X64FunctionCode {
)[0]; )[0];
self.value_stack.push(ret); self.value_stack.push(ret);
let tmpg1 = self.machine.acquire_temp_gpr().unwrap();
a.emit_mov(Size::S32, loc, Location::GPR(tmpg1));
a.emit_and(Size::S32, Location::Imm32(0xFF), Location::GPR(tmpg1));
Self::emit_relaxed_zx_sx( Self::emit_relaxed_zx_sx(
a, a,
&mut self.machine, &mut self.machine,
Assembler::emit_movsx, Assembler::emit_movsx,
Size::S8, Size::S8,
Location::GPR(tmpg1), loc,
Size::S64, Size::S64,
ret, ret,
); );
self.machine.release_temp_gpr(tmpg1);
} }
Operator::I64Extend16S => { Operator::I64Extend16S => {
let loc = let loc =
@ -3034,18 +3024,15 @@ impl FunctionCodeGenerator<CodegenError> for X64FunctionCode {
)[0]; )[0];
self.value_stack.push(ret); self.value_stack.push(ret);
let tmpg1 = self.machine.acquire_temp_gpr().unwrap();
a.emit_mov(Size::S32, loc, Location::GPR(tmpg1));
Self::emit_relaxed_zx_sx( Self::emit_relaxed_zx_sx(
a, a,
&mut self.machine, &mut self.machine,
Assembler::emit_movsx, Assembler::emit_movsx,
Size::S16, Size::S16,
Location::GPR(tmpg1), loc,
Size::S64, Size::S64,
ret, ret,
); );
self.machine.release_temp_gpr(tmpg1);
} }
Operator::I64Extend32S => { Operator::I64Extend32S => {
let loc = let loc =
@ -3057,18 +3044,15 @@ impl FunctionCodeGenerator<CodegenError> for X64FunctionCode {
)[0]; )[0];
self.value_stack.push(ret); self.value_stack.push(ret);
let tmpg1 = self.machine.acquire_temp_gpr().unwrap();
a.emit_mov(Size::S32, loc, Location::GPR(tmpg1));
Self::emit_relaxed_zx_sx( Self::emit_relaxed_zx_sx(
a, a,
&mut self.machine, &mut self.machine,
Assembler::emit_movsx, Assembler::emit_movsx,
Size::S32, Size::S32,
Location::GPR(tmpg1), loc,
Size::S64, Size::S64,
ret, ret,
); );
self.machine.release_temp_gpr(tmpg1);
} }
Operator::I32WrapI64 => { Operator::I32WrapI64 => {
let loc = let loc =