From 81d538ade29ca45fcece848cb9bb4047a752ab92 Mon Sep 17 00:00:00 2001 From: losfair Date: Tue, 15 Oct 2019 22:00:33 +0800 Subject: [PATCH] Fix disp < 0 case. --- .../src/translator_aarch64.rs | 94 +++++++++---------- 1 file changed, 47 insertions(+), 47 deletions(-) diff --git a/lib/singlepass-backend/src/translator_aarch64.rs b/lib/singlepass-backend/src/translator_aarch64.rs index 0c373a9e5..d2ae87a8b 100644 --- a/lib/singlepass-backend/src/translator_aarch64.rs +++ b/lib/singlepass-backend/src/translator_aarch64.rs @@ -226,7 +226,7 @@ macro_rules! binop_gpr_mem { if disp >= 0 { dynasm!($assembler ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!($assembler ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!($assembler ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!($assembler ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!($assembler ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!($assembler ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!($assembler ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!($assembler ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, after; data: ; .dword x as i32; after: ; ldr w_tmp1, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, after; data: ; .qword x as i64; after: ; ldr x_tmp1, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, after; data: ; .dword x as i32; after: ; ldr w_tmp1, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, after; data: ; .dword x as i32; after: ; ldr w_tmp1, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, after @@ -813,7 +813,7 @@ impl Emitter for Assembler { if disp >= 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, after @@ -837,7 +837,7 @@ impl Emitter for Assembler { if disp >= 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(self ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(assembler ; disp: ; .dword disp as i32 ; ldr w_tmp3, = 0 { dynasm!(assembler ; disp: ; .dword disp as i32 ; ldr w_tmp3,