mirror of
https://github.com/fluencelabs/wasmer
synced 2025-06-25 14:41:32 +00:00
Fixes and some floating point operations.
This commit is contained in:
losfair
@ -676,6 +676,17 @@ impl X64FunctionCode {
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Ok(())
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}
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fn emit_reinterpret(value_stack: &mut ValueStack, in_ty: WpType, out_ty: WpType) -> Result<(), CodegenError> {
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let val = value_stack.pop()?;
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if val.ty != in_ty {
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return Err(CodegenError {
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message: "reinterpret type mismatch"
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});
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}
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value_stack.push(out_ty);
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Ok(())
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}
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/// Emits a unary operator.
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fn emit_unop<F: FnOnce(&mut Assembler, &ValueStack, Register)>(
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assembler: &mut Assembler,
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@ -1117,7 +1128,7 @@ impl X64FunctionCode {
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Some(x) => x,
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None => {
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return Err(CodegenError {
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message: "no frame",
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message: "no frame (else)",
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})
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}
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};
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@ -1163,7 +1174,7 @@ impl X64FunctionCode {
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Some(x) => x,
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None => {
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return Err(CodegenError {
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message: "no frame",
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message: "no frame (block end)",
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})
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}
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};
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@ -1651,9 +1662,17 @@ impl FunctionCodeGenerator for X64FunctionCode {
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Operator::Block { .. } | Operator::Loop { .. } | Operator::If { .. } => {
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self.unreachable_depth += 1;
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}
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Operator::End | Operator::Else => {
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Operator::End => {
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self.unreachable_depth -= 1;
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}
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Operator::Else => {
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// We are in a reachable true branch
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if self.unreachable_depth == 1 {
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if let Some(IfElseState::If(_)) = self.control_stack.as_ref().unwrap().frames.last().map(|x| x.if_else) {
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self.unreachable_depth -= 1;
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}
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}
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}
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_ => {}
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}
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if self.unreachable_depth > 0 {
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@ -1981,6 +2000,18 @@ impl FunctionCodeGenerator for X64FunctionCode {
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},
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)?;
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}
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Operator::I32Xor => {
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Self::emit_binop_i32(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; xor Rd(left as u8), Rd(right as u8)
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);
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},
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)?;
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}
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Operator::I32Eq => {
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Self::emit_binop_i32(
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assembler,
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@ -2399,6 +2430,18 @@ impl FunctionCodeGenerator for X64FunctionCode {
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},
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)?;
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}
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Operator::I64Xor => {
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Self::emit_binop_i64(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; xor Rq(left as u8), Rq(right as u8)
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);
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},
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)?;
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}
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Operator::I64Eq => {
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Self::emit_binop(
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assembler,
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@ -3331,6 +3374,361 @@ impl FunctionCodeGenerator for X64FunctionCode {
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WpType::I64,
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)?;
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}
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Operator::F32Const { value } => {
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let location = self.value_stack.push(WpType::F32);
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match location {
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ValueLocation::Register(x) => {
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let reg = Register::from_scratch_reg(x);
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dynasm!(
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assembler
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; mov Rd(reg as u8), value.bits() as i32
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);
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}
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ValueLocation::Stack => {
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dynasm!(
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assembler
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; push value.bits() as i32
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);
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}
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}
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}
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Operator::F64Const { value } => {
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let location = self.value_stack.push(WpType::F64);
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match location {
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ValueLocation::Register(x) => {
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let reg = Register::from_scratch_reg(x);
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dynasm!(
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assembler
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; mov Rq(reg as u8), QWORD value.bits() as i64
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);
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}
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ValueLocation::Stack => {
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dynasm!(
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assembler
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; mov rax, QWORD value.bits() as i64
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; push rax
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);
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}
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}
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}
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Operator::F32Load { memarg } => {
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Self::emit_memory_load(
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assembler,
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&mut self.value_stack,
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|assembler, reg| {
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dynasm!(
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assembler
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; mov Rd(reg as u8), [Rq(reg as u8) + memarg.offset as i32]
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);
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},
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WpType::F32,
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)?;
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}
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Operator::F32Store { memarg } => {
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Self::emit_memory_store(
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assembler,
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&mut self.value_stack,
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|assembler, addr_reg, value_reg| {
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dynasm!(
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assembler
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; mov [Rq(addr_reg as u8) + memarg.offset as i32], Rd(value_reg as u8)
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);
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},
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WpType::F32,
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)?;
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}
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Operator::F64Load { memarg } => {
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Self::emit_memory_load(
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assembler,
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&mut self.value_stack,
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|assembler, reg| {
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dynasm!(
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assembler
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; mov Rq(reg as u8), [Rq(reg as u8) + memarg.offset as i32]
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);
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},
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WpType::F64,
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)?;
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}
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Operator::F64Store { memarg } => {
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Self::emit_memory_store(
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assembler,
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&mut self.value_stack,
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|assembler, addr_reg, value_reg| {
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dynasm!(
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assembler
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; mov [Rq(addr_reg as u8) + memarg.offset as i32], Rq(value_reg as u8)
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);
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},
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WpType::F64,
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)?;
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}
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Operator::I32ReinterpretF32 => {
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Self::emit_reinterpret(&mut self.value_stack, WpType::F32, WpType::I32)?;
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}
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Operator::F32ReinterpretI32 => {
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Self::emit_reinterpret(&mut self.value_stack, WpType::I32, WpType::F32)?;
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}
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Operator::I64ReinterpretF64 => {
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Self::emit_reinterpret(&mut self.value_stack, WpType::F64, WpType::I64)?;
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}
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Operator::F64ReinterpretI64 => {
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Self::emit_reinterpret(&mut self.value_stack, WpType::I64, WpType::F64)?;
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}
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Operator::F32Add => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movd xmm1, Rd(left as u8)
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; movd xmm2, Rd(right as u8)
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; addss xmm1, xmm2
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; movd Rd(left as u8), xmm1
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);
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},
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WpType::F32,
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WpType::F32,
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)?;
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}
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Operator::F32Sub => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movd xmm1, Rd(left as u8)
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; movd xmm2, Rd(right as u8)
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; subss xmm1, xmm2
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; movd Rd(left as u8), xmm1
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);
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},
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WpType::F32,
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WpType::F32,
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)?;
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}
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Operator::F32Mul => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movd xmm1, Rd(left as u8)
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; movd xmm2, Rd(right as u8)
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; mulss xmm1, xmm2
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; movd Rd(left as u8), xmm1
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);
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},
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WpType::F32,
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WpType::F32,
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)?;
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}
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Operator::F32Div => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movd xmm1, Rd(left as u8)
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; movd xmm2, Rd(right as u8)
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; divss xmm1, xmm2
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; movd Rd(left as u8), xmm1
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);
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},
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WpType::F32,
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WpType::F32,
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)?;
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}
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Operator::F32Max => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movd xmm1, Rd(left as u8)
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; movd xmm2, Rd(right as u8)
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; maxss xmm1, xmm2
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; movd Rd(left as u8), xmm1
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);
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},
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WpType::F32,
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WpType::F32,
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)?;
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}
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Operator::F32Min => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movd xmm1, Rd(left as u8)
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; movd xmm2, Rd(right as u8)
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; minss xmm1, xmm2
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; movd Rd(left as u8), xmm1
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);
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},
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WpType::F32,
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WpType::F32,
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)?;
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}
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Operator::F32Eq => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movd xmm1, Rd(left as u8)
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; movd xmm2, Rd(right as u8)
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; cmpeqss xmm1, xmm2
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; movd Rd(left as u8), xmm1
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; and Rd(left as u8), 1
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);
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},
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WpType::F32,
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WpType::I32,
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)?;
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}
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Operator::F32Ne => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movd xmm1, Rd(left as u8)
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; movd xmm2, Rd(right as u8)
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; cmpneqss xmm1, xmm2
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; movd Rd(left as u8), xmm1
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; and Rd(left as u8), 1
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);
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},
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WpType::F32,
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WpType::I32,
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)?;
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}
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Operator::F32Gt => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movd xmm1, Rd(left as u8)
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; movd xmm2, Rd(right as u8)
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; vcmpgtss xmm1, xmm1, xmm2
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; movd Rd(left as u8), xmm1
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; and Rd(left as u8), 1
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);
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},
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WpType::F32,
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WpType::I32,
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)?;
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}
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Operator::F32Ge => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movd xmm1, Rd(left as u8)
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; movd xmm2, Rd(right as u8)
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; vcmpgess xmm1, xmm1, xmm2
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; movd Rd(left as u8), xmm1
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; and Rd(left as u8), 1
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);
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},
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WpType::F32,
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WpType::I32,
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)?;
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}
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Operator::F32Lt => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movd xmm1, Rd(left as u8)
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; movd xmm2, Rd(right as u8)
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; cmpltss xmm1, xmm2
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; movd Rd(left as u8), xmm1
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; and Rd(left as u8), 1
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);
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},
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WpType::F32,
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WpType::I32,
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)?;
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}
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Operator::F32Le => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movd xmm1, Rd(left as u8)
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; movd xmm2, Rd(right as u8)
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; cmpless xmm1, xmm2
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; movd Rd(left as u8), xmm1
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; and Rd(left as u8), 1
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);
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},
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WpType::F32,
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WpType::I32,
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)?;
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}
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Operator::F32Sqrt => {
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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dynasm!(
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assembler
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; movd xmm1, Rd(reg as u8)
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; sqrtss xmm1, xmm1
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; movd Rd(reg as u8), xmm1
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);
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},
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WpType::F32,
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WpType::F32
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)?;
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}
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Operator::F32Abs => {
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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dynasm!(
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assembler
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; and Rd(reg as u8), 0x7fffffffu32 as i32
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);
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},
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WpType::F32,
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WpType::F32
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)?;
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}
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Operator::F32Neg => {
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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dynasm!(
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assembler
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; btc Rd(reg as u8), 31
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);
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},
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WpType::F32,
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WpType::F32
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)?;
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}
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Operator::Nop => {}
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Operator::MemorySize { reserved } => {
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let memory_index = MemoryIndex::new(reserved as usize);
|
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|
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Block a user