mirror of
https://github.com/fluencelabs/wasmer
synced 2025-06-25 06:31:32 +00:00
Implemented more floating point operations.
This commit is contained in:
losfair
@ -3475,6 +3475,206 @@ impl FunctionCodeGenerator for X64FunctionCode {
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Operator::F64ReinterpretI64 => {
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Self::emit_reinterpret(&mut self.value_stack, WpType::I64, WpType::F64)?;
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}
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Operator::F32ConvertSI32 => {
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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dynasm!(
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assembler
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; cvtsi2ss xmm1, Rd(reg as u8)
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; movd Rd(reg as u8), xmm1
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);
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},
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WpType::I32,
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WpType::F32,
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)?;
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}
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Operator::F32ConvertUI32 => {
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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dynasm!(
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assembler
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; mov Rd(reg as u8), Rd(reg as u8) // clear upper 32 bits
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; cvtsi2ss xmm1, Rq(reg as u8)
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; movd Rd(reg as u8), xmm1
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);
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},
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WpType::I32,
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WpType::F32,
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)?;
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}
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Operator::F32ConvertSI64 => {
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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dynasm!(
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assembler
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; cvtsi2ss xmm1, Rq(reg as u8)
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; movd Rd(reg as u8), xmm1
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);
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},
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WpType::I64,
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WpType::F32,
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)?;
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}
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/*
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0: 48 85 ff test %rdi,%rdi
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3: 78 0b js 10 <ulong2double+0x10>
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5: c4 e1 fb 2a c7 vcvtsi2sd %rdi,%xmm0,%xmm0
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a: c3 retq
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b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1)
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10: 48 89 f8 mov %rdi,%rax
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13: 83 e7 01 and $0x1,%edi
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16: 48 d1 e8 shr %rax
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19: 48 09 f8 or %rdi,%rax
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1c: c4 e1 fb 2a c0 vcvtsi2sd %rax,%xmm0,%xmm0
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21: c5 fb 58 c0 vaddsd %xmm0,%xmm0,%xmm0
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25: c3 retq
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*/
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Operator::F32ConvertUI64 => {
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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dynasm!(
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assembler
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; test Rq(reg as u8), Rq(reg as u8)
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; js >do_convert
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// fast path: positive as signed
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; cvtsi2ss xmm1, Rq(reg as u8)
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; movd Rd(reg as u8), xmm1
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; jmp >end_convert
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; do_convert:
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// use r15 as temporary register
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; movq xmm5, r15
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; mov r15, Rq(reg as u8)
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; and r15, 1
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; shr Rq(reg as u8), 1
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; or Rq(reg as u8), r15
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; cvtsi2ss xmm1, Rq(reg as u8)
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; addsd xmm1, xmm1
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; movq r15, xmm5
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; movd Rd(reg as u8), xmm1
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; end_convert:
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);
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},
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WpType::I64,
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WpType::F32,
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)?;
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}
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Operator::F64ConvertSI32 => {
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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dynasm!(
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assembler
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; cvtsi2sd xmm1, Rd(reg as u8)
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; movq Rq(reg as u8), xmm1
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);
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},
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WpType::I32,
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WpType::F64,
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)?;
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}
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Operator::F64ConvertUI32 => {
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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dynasm!(
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assembler
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; mov Rd(reg as u8), Rd(reg as u8) // clear upper 32 bits
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; cvtsi2sd xmm1, Rq(reg as u8)
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; movq Rq(reg as u8), xmm1
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);
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},
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WpType::I32,
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WpType::F64,
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)?;
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}
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Operator::F64ConvertSI64 => {
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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dynasm!(
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assembler
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; cvtsi2sd xmm1, Rq(reg as u8)
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; movq Rq(reg as u8), xmm1
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);
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},
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WpType::I64,
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WpType::F64,
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)?;
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}
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Operator::F64ConvertUI64 => {
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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dynasm!(
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assembler
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; test Rq(reg as u8), Rq(reg as u8)
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; js >do_convert
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// fast path: positive as signed
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; cvtsi2sd xmm1, Rq(reg as u8)
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; movq Rq(reg as u8), xmm1
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; jmp >end_convert
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; do_convert:
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// use r15 as temporary register
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; movq xmm5, r15
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; mov r15, Rq(reg as u8)
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; and r15, 1
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; shr Rq(reg as u8), 1
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; or Rq(reg as u8), r15
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; cvtsi2sd xmm1, Rq(reg as u8)
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; addsd xmm1, xmm1
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; movq r15, xmm5
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; movq Rq(reg as u8), xmm1
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; end_convert:
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);
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},
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WpType::I64,
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WpType::F64,
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)?;
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}
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Operator::F64PromoteF32 => {
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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dynasm!(
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assembler
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; movd xmm1, Rd(reg as u8)
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; cvtss2sd xmm1, xmm1
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; movq Rq(reg as u8), xmm1
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);
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},
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WpType::F32,
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WpType::F64,
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)?;
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}
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Operator::F32DemoteF64 => {
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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dynasm!(
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assembler
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; movq xmm1, Rq(reg as u8)
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; cvtsd2ss xmm1, xmm1
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; movd Rd(reg as u8), xmm1
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);
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},
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WpType::F64,
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WpType::F32,
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)?;
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}
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Operator::F32Add => {
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Self::emit_binop(
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assembler,
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@ -3685,6 +3885,29 @@ impl FunctionCodeGenerator for X64FunctionCode {
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WpType::I32,
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)?;
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}
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Operator::F32Copysign => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movd xmm1, Rd(left as u8)
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; movd xmm2, Rd(right as u8)
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; mov eax, 0x7fffffffu32 as i32
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; movd xmm3, eax
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; pand xmm1, xmm3
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; mov eax, 0x80000000u32 as i32
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; movd xmm3, eax
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; pand xmm2, xmm3
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; por xmm1, xmm2
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; movd Rd(left as u8), xmm1
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);
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},
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WpType::F32,
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WpType::F32,
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)?;
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}
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Operator::F32Sqrt => {
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Self::emit_unop(
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assembler,
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@ -3729,6 +3952,287 @@ impl FunctionCodeGenerator for X64FunctionCode {
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WpType::F32
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)?;
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}
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Operator::F64Add => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movq xmm1, Rq(left as u8)
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; movq xmm2, Rq(right as u8)
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; addsd xmm1, xmm2
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; movq Rq(left as u8), xmm1
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);
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},
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WpType::F64,
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WpType::F64,
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)?;
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}
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Operator::F64Sub => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movq xmm1, Rq(left as u8)
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; movq xmm2, Rq(right as u8)
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; subsd xmm1, xmm2
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; movq Rq(left as u8), xmm1
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);
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},
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WpType::F64,
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WpType::F64,
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)?;
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}
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Operator::F64Mul => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movq xmm1, Rq(left as u8)
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; movq xmm2, Rq(right as u8)
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; mulsd xmm1, xmm2
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; movq Rq(left as u8), xmm1
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);
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},
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WpType::F64,
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WpType::F64,
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)?;
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}
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Operator::F64Div => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movq xmm1, Rq(left as u8)
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; movq xmm2, Rq(right as u8)
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; divsd xmm1, xmm2
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; movq Rq(left as u8), xmm1
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);
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},
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WpType::F64,
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WpType::F64,
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)?;
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}
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Operator::F64Max => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movq xmm1, Rq(left as u8)
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; movq xmm2, Rq(right as u8)
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; maxsd xmm1, xmm2
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; movq Rq(left as u8), xmm1
|
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);
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},
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WpType::F64,
|
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WpType::F64,
|
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)?;
|
||||
}
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Operator::F64Min => {
|
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Self::emit_binop(
|
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assembler,
|
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; movq xmm1, Rq(left as u8)
|
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; movq xmm2, Rq(right as u8)
|
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; minsd xmm1, xmm2
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; movq Rq(left as u8), xmm1
|
||||
);
|
||||
},
|
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WpType::F64,
|
||||
WpType::F64,
|
||||
)?;
|
||||
}
|
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Operator::F64Eq => {
|
||||
Self::emit_binop(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, value_stack, left, right| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; movq xmm1, Rq(left as u8)
|
||||
; movq xmm2, Rq(right as u8)
|
||||
; cmpeqsd xmm1, xmm2
|
||||
; movd Rd(left as u8), xmm1
|
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; and Rd(left as u8), 1
|
||||
);
|
||||
},
|
||||
WpType::F64,
|
||||
WpType::I32,
|
||||
)?;
|
||||
}
|
||||
Operator::F64Ne => {
|
||||
Self::emit_binop(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, value_stack, left, right| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; movq xmm1, Rq(left as u8)
|
||||
; movq xmm2, Rq(right as u8)
|
||||
; cmpneqsd xmm1, xmm2
|
||||
; movd Rd(left as u8), xmm1
|
||||
; and Rd(left as u8), 1
|
||||
);
|
||||
},
|
||||
WpType::F64,
|
||||
WpType::I32,
|
||||
)?;
|
||||
}
|
||||
Operator::F64Gt => {
|
||||
Self::emit_binop(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, value_stack, left, right| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; movq xmm1, Rq(left as u8)
|
||||
; movq xmm2, Rq(right as u8)
|
||||
; vcmpgtsd xmm1, xmm1, xmm2
|
||||
; movd Rd(left as u8), xmm1
|
||||
; and Rd(left as u8), 1
|
||||
);
|
||||
},
|
||||
WpType::F64,
|
||||
WpType::I32,
|
||||
)?;
|
||||
}
|
||||
Operator::F64Ge => {
|
||||
Self::emit_binop(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, value_stack, left, right| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; movq xmm1, Rq(left as u8)
|
||||
; movq xmm2, Rq(right as u8)
|
||||
; vcmpgesd xmm1, xmm1, xmm2
|
||||
; movd Rd(left as u8), xmm1
|
||||
; and Rd(left as u8), 1
|
||||
);
|
||||
},
|
||||
WpType::F64,
|
||||
WpType::I32,
|
||||
)?;
|
||||
}
|
||||
Operator::F64Lt => {
|
||||
Self::emit_binop(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, value_stack, left, right| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; movq xmm1, Rq(left as u8)
|
||||
; movq xmm2, Rq(right as u8)
|
||||
; cmpltsd xmm1, xmm2
|
||||
; movd Rd(left as u8), xmm1
|
||||
; and Rd(left as u8), 1
|
||||
);
|
||||
},
|
||||
WpType::F64,
|
||||
WpType::I32,
|
||||
)?;
|
||||
}
|
||||
Operator::F64Le => {
|
||||
Self::emit_binop(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, value_stack, left, right| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; movq xmm1, Rq(left as u8)
|
||||
; movq xmm2, Rq(right as u8)
|
||||
; cmplesd xmm1, xmm2
|
||||
; movd Rd(left as u8), xmm1
|
||||
; and Rd(left as u8), 1
|
||||
);
|
||||
},
|
||||
WpType::F64,
|
||||
WpType::I32,
|
||||
)?;
|
||||
}
|
||||
Operator::F64Copysign => {
|
||||
Self::emit_binop(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, value_stack, left, right| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; movq xmm1, Rq(left as u8)
|
||||
; movq xmm2, Rq(right as u8)
|
||||
; mov rax, QWORD 0x7fffffffffffffffu64 as i64
|
||||
; movq xmm3, rax
|
||||
; pand xmm1, xmm3
|
||||
; mov rax, QWORD 0x8000000000000000u64 as i64
|
||||
; movq xmm3, rax
|
||||
; pand xmm2, xmm3
|
||||
; por xmm1, xmm2
|
||||
; movq Rq(left as u8), xmm1
|
||||
);
|
||||
},
|
||||
WpType::F64,
|
||||
WpType::F64,
|
||||
)?;
|
||||
}
|
||||
Operator::F64Sqrt => {
|
||||
Self::emit_unop(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, value_stack, reg| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; movq xmm1, Rq(reg as u8)
|
||||
; sqrtsd xmm1, xmm1
|
||||
; movq Rq(reg as u8), xmm1
|
||||
);
|
||||
},
|
||||
WpType::F64,
|
||||
WpType::F64
|
||||
)?;
|
||||
}
|
||||
Operator::F64Abs => {
|
||||
Self::emit_unop(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, value_stack, reg| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; movq xmm1, Rq(reg as u8)
|
||||
; mov rax, QWORD 0x7fffffffffffffff
|
||||
; movq xmm2, rax
|
||||
; por xmm1, xmm2
|
||||
; movq Rq(reg as u8), xmm1
|
||||
);
|
||||
},
|
||||
WpType::F64,
|
||||
WpType::F64
|
||||
)?;
|
||||
}
|
||||
Operator::F64Neg => {
|
||||
Self::emit_unop(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, value_stack, reg| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; btc Rq(reg as u8), 63
|
||||
);
|
||||
},
|
||||
WpType::F64,
|
||||
WpType::F64
|
||||
)?;
|
||||
}
|
||||
Operator::Nop => {}
|
||||
Operator::MemorySize { reserved } => {
|
||||
let memory_index = MemoryIndex::new(reserved as usize);
|
||||
|
||||
Reference in New Issue
Block a user