<!DOCTYPE html><htmllang="en"><head><metacharset="utf-8"><metaname="viewport"content="width=device-width, initial-scale=1.0"><metaname="generator"content="rustdoc"><metaname="description"content="API documentation for the Rust `FeatureInfo` struct in crate `raw_cpuid`."><metaname="keywords"content="rust, rustlang, rust-lang, FeatureInfo"><title>raw_cpuid::FeatureInfo - Rust</title><linkrel="stylesheet"type="text/css"href="../normalize.css"><linkrel="stylesheet"type="text/css"href="../rustdoc.css"id="mainThemeStyle"><linkrel="stylesheet"type="text/css"href="../dark.css"><linkrel="stylesheet"type="text/css"href="../light.css"id="themeStyle"><scriptsrc="../storage.js"></script><noscript><linkrel="stylesheet"href="../noscript.css"></noscript><linkrel="shortcut icon"href="../favicon.ico"><styletype="text/css">#crate-search{background-image:url("../down-arrow.svg");}</style></head><bodyclass="rustdoc struct"><!--[if lte IE 8]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><navclass="sidebar"><divclass="sidebar-menu">☰</div><ahref='../raw_cpuid/index.html'><divclass='logo-container'><imgsrc='../rust-logo.png'alt='logo'></div></a><pclass='location'>Struct FeatureInfo</p><divclass="sidebar-elems"><divclass="block items"><aclass="sidebar-title"href="#methods">Methods</a><divclass="sidebar-links"><ahref="#method.brand_index">brand_index</a><ahref="#method.cflush_cache_line_size">cflush_cache_line_size</a><ahref="#method.extended_family_id">extended_family_id</a><ahref="#method.extended_model_id">extended_model_id</a><ahref="#method.family_id">family_id</a><ahref="#method.has_acpi">has_acpi</a><ahref="#method.has_aesni">has_aesni</a><ahref="#method.has_apic">has_apic</a><ahref="#method.has_avx">has_avx</a><ahref="#method.has_clflush">has_clflush</a><ahref="#method.has_cmov">has_cmov</a><ahref="#method.has_cmpxchg16b">has_cmpxchg16b</a><ahref="#method.has_cmpxchg8b">has_cmpxchg8b</a><ahref="#method.has_cnxtid">has_cnxtid</a><ahref="#method.has_cpl">has_cpl</a><ahref="#method.has_dca">has_dca</a><ahref="#method.has_de">has_de</a><ahref="#method.has_ds">has_ds</a><ahref="#method.has_ds_area">has_ds_area</a><ahref="#method.has_eist">has_eist</a><ahref="#method.has_f16c">has_f16c</a><ahref="#method.has_fma">has_fma</a><ahref="#method.has_fpu">has_fpu</a><ahref="#method.has_fxsave_fxstor">has_fxsave_fxstor</a><ahref="#method.has_htt">has_htt</a><ahref="#method.has_mca">has_mca</a><ahref="#method.has_mce">has_mce</a><ahref="#method.has_mmx">has_mmx</a><ahref="#method.has_monitor_mwait">has_monitor_mwait</a><ahref="#method.has_movbe">has_movbe</a><ahref="#method.has_msr">has_msr</a><ahref="#method.has_mtrr">has_mtrr</a><ahref="#method.has_oxsave">has_oxsave</a><ahref="#method.has_pae">has_pae</a><ahref="#method.has_pat">has_pat</a><ahref="#method.has_pbe">has_pbe</a><ahref="#method.has_pcid">has_pcid</a><ahref="#method.has_pclmulqdq">has_pclmulqdq</a><ahref="#method.has_pdcm">has_pdcm</a><ahref="#method.has_pge">has_pge</a><ahref="#method.has_popcnt">has_popcnt</a><ahref="#method.has_pse">has_pse</a><ahref="#method.has_pse36">has_pse36</a><ahref="#method.has_psn">has_psn</a><ahref="#method.has_rdrand">has_rdrand</a><ahref="#method.has_smx">has_smx</a><ahref="#method.has_ss">has_ss</a><ahref="#method.has_sse">has_sse</a><ahref="#method.has_sse2">has_sse2</a><ahref="#method.has_sse3">has_sse3</a><ahref="#method.has_sse41">has_sse41</a><ahref="#method.has_sse42">has_sse42</a><ahref="#method.has_ssse3">has_ssse3</a><ahref="#method.has_sysenter_sysexit">has_sysenter_sysexit</a><ahref="#method.has_tm">has_tm</a><ahref="#method.has_tm2">has_tm2</a><ahref="#method.has_tsc">has_tsc</a><ahref="#method.has_tsc_deadline">has_tsc_deadline</a><ahref="#method.has_vme">has_vme</a><ahref="#method.has_vmx">has_vmx</a><ahref="#method.has_x2apic">has_x2apic</a><ahref="#method.has_xsave">has_xsave</a><ahref="#method.initial_local_apic_id">initial_local_apic_id</a><ahref="#method.max_l
</div><h4id='method.max_logical_processor_ids'class="method"><codeid='max_logical_processor_ids.v'>pub fn <ahref='#method.max_logical_processor_ids'class='fnname'>max_logical_processor_ids</a>(&self) -> u8</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#1317-1319'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Maximum number of addressable IDs for logical processors in this physical package.</p>
</div><h4id='method.has_sse3'class="method"><codeid='has_sse3.v'>pub fn <ahref='#method.has_sse3'class='fnname'>has_sse3</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the processor supports this technology.</p>
</div><h4id='method.has_pclmulqdq'class="method"><codeid='has_pclmulqdq.v'>pub fn <ahref='#method.has_pclmulqdq'class='fnname'>has_pclmulqdq</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>PCLMULQDQ. A value of 1 indicates the processor supports the PCLMULQDQ instruction</p>
</div><h4id='method.has_ds_area'class="method"><codeid='has_ds_area.v'>pub fn <ahref='#method.has_ds_area'class='fnname'>has_ds_area</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>64-bit DS Area. A value of 1 indicates the processor supports DS area using 64-bit layout</p>
</div><h4id='method.has_monitor_mwait'class="method"><codeid='has_monitor_mwait.v'>pub fn <ahref='#method.has_monitor_mwait'class='fnname'>has_monitor_mwait</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>MONITOR/MWAIT. A value of 1 indicates the processor supports this feature.</p>
</div><h4id='method.has_cpl'class="method"><codeid='has_cpl.v'>pub fn <ahref='#method.has_cpl'class='fnname'>has_cpl</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>CPL Qualified Debug Store. A value of 1 indicates the processor supports the extensions to the Debug Store feature to allow for branch message storage qualified by CPL.</p>
</div><h4id='method.has_vmx'class="method"><codeid='has_vmx.v'>pub fn <ahref='#method.has_vmx'class='fnname'>has_vmx</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Virtual Machine Extensions. A value of 1 indicates that the processor supports this technology.</p>
</div><h4id='method.has_smx'class="method"><codeid='has_smx.v'>pub fn <ahref='#method.has_smx'class='fnname'>has_smx</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Safer Mode Extensions. A value of 1 indicates that the processor supports this technology. See Chapter 5, Safer Mode Extensions Reference.</p>
</div><h4id='method.has_eist'class="method"><codeid='has_eist.v'>pub fn <ahref='#method.has_eist'class='fnname'>has_eist</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Enhanced Intel SpeedStep® technology. A value of 1 indicates that the processor supports this technology.</p>
</div><h4id='method.has_tm2'class="method"><codeid='has_tm2.v'>pub fn <ahref='#method.has_tm2'class='fnname'>has_tm2</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Thermal Monitor 2. A value of 1 indicates whether the processor supports this technology.</p>
</div><h4id='method.has_ssse3'class="method"><codeid='has_ssse3.v'>pub fn <ahref='#method.has_ssse3'class='fnname'>has_ssse3</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>A value of 1 indicates the presence of the Supplemental Streaming SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction extensions are not present in the processor</p>
</div><h4id='method.has_cnxtid'class="method"><codeid='has_cnxtid.v'>pub fn <ahref='#method.has_cnxtid'class='fnname'>has_cnxtid</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>L1 Context ID. A value of 1 indicates the L1 data cache mode can be set to either adaptive mode or shared mode. A value of 0 indicates this feature is not supported. See definition of the IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for details.</p>
</div><h4id='method.has_fma'class="method"><codeid='has_fma.v'>pub fn <ahref='#method.has_fma'class='fnname'>has_fma</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>A value of 1 indicates the processor supports FMA extensions using YMM state.</p>
</div><h4id='method.has_cmpxchg16b'class="method"><codeid='has_cmpxchg16b.v'>pub fn <ahref='#method.has_cmpxchg16b'class='fnname'>has_cmpxchg16b</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>CMPXCHG16B Available. A value of 1 indicates that the feature is available. See the CMPXCHG8B/CMPXCHG16B Compare and Exchange Bytes section. 14</p>
</div><h4id='method.has_pdcm'class="method"><codeid='has_pdcm.v'>pub fn <ahref='#method.has_pdcm'class='fnname'>has_pdcm</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Perfmon and Debug Capability: A value of 1 indicates the processor supports the performance and debug feature indication MSR IA32_PERF_CAPABILITIES.</p>
</div><h4id='method.has_pcid'class="method"><codeid='has_pcid.v'>pub fn <ahref='#method.has_pcid'class='fnname'>has_pcid</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Process-context identifiers. A value of 1 indicates that the processor supports PCIDs and the software may set CR4.PCIDE to 1.</p>
</div><h4id='method.has_dca'class="method"><codeid='has_dca.v'>pub fn <ahref='#method.has_dca'class='fnname'>has_dca</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>A value of 1 indicates the processor supports the ability to prefetch data from a memory mapped device.</p>
</div><h4id='method.has_sse41'class="method"><codeid='has_sse41.v'>pub fn <ahref='#method.has_sse41'class='fnname'>has_sse41</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>A value of 1 indicates that the processor supports SSE4.1.</p>
</div><h4id='method.has_sse42'class="method"><codeid='has_sse42.v'>pub fn <ahref='#method.has_sse42'class='fnname'>has_sse42</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>A value of 1 indicates that the processor supports SSE4.2.</p>
</div><h4id='method.has_x2apic'class="method"><codeid='has_x2apic.v'>pub fn <ahref='#method.has_x2apic'class='fnname'>has_x2apic</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>A value of 1 indicates that the processor supports x2APIC feature.</p>
</div><h4id='method.has_movbe'class="method"><codeid='has_movbe.v'>pub fn <ahref='#method.has_movbe'class='fnname'>has_movbe</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>A value of 1 indicates that the processor supports MOVBE instruction.</p>
</div><h4id='method.has_popcnt'class="method"><codeid='has_popcnt.v'>pub fn <ahref='#method.has_popcnt'class='fnname'>has_popcnt</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>A value of 1 indicates that the processor supports the POPCNT instruction.</p>
</div><h4id='method.has_tsc_deadline'class="method"><codeid='has_tsc_deadline.v'>pub fn <ahref='#method.has_tsc_deadline'class='fnname'>has_tsc_deadline</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>A value of 1 indicates that the processors local APIC timer supports one-shot operation using a TSC deadline value.</p>
</div><h4id='method.has_aesni'class="method"><codeid='has_aesni.v'>pub fn <ahref='#method.has_aesni'class='fnname'>has_aesni</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>A value of 1 indicates that the processor supports the AESNI instruction extensions.</p>
</div><h4id='method.has_xsave'class="method"><codeid='has_xsave.v'>pub fn <ahref='#method.has_xsave'class='fnname'>has_xsave</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>A value of 1 indicates that the processor supports the XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV instructions, and XCR0.</p>
</div><h4id='method.has_oxsave'class="method"><codeid='has_oxsave.v'>pub fn <ahref='#method.has_oxsave'class='fnname'>has_oxsave</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>A value of 1 indicates that the OS has enabled XSETBV/XGETBV instructions to access XCR0, and support for processor extended state management using XSAVE/XRSTOR.</p>
</div><h4id='method.has_avx'class="method"><codeid='has_avx.v'>pub fn <ahref='#method.has_avx'class='fnname'>has_avx</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>A value of 1 indicates the processor supports the AVX instruction extensions.</p>
</div><h4id='method.has_f16c'class="method"><codeid='has_f16c.v'>pub fn <ahref='#method.has_f16c'class='fnname'>has_f16c</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>A value of 1 indicates that processor supports 16-bit floating-point conversion instructions.</p>
</div><h4id='method.has_rdrand'class="method"><codeid='has_rdrand.v'>pub fn <ahref='#method.has_rdrand'class='fnname'>has_rdrand</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>A value of 1 indicates that processor supports RDRAND instruction.</p>
</div><h4id='method.has_fpu'class="method"><codeid='has_fpu.v'>pub fn <ahref='#method.has_fpu'class='fnname'>has_fpu</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Floating Point Unit On-Chip. The processor contains an x87 FPU.</p>
</div><h4id='method.has_vme'class="method"><codeid='has_vme.v'>pub fn <ahref='#method.has_vme'class='fnname'>has_vme</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, including CR4.VME for controlling the feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirection, expansion of the TSS with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.</p>
</div><h4id='method.has_de'class="method"><codeid='has_de.v'>pub fn <ahref='#method.has_de'class='fnname'>has_de</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Debugging Extensions. Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional trapping of accesses to DR4 and DR5.</p>
</div><h4id='method.has_pse'class="method"><codeid='has_pse.v'>pub fn <ahref='#method.has_pse'class='fnname'>has_pse</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Page Size Extension. Large pages of size 4 MByte are supported, including CR4.PSE for controlling the feature, the defined dirty bit in PDE (Page Directory Entries), optional reserved bit trapping in CR3, PDEs, and PTEs.</p>
</div><h4id='method.has_tsc'class="method"><codeid='has_tsc.v'>pub fn <ahref='#method.has_tsc'class='fnname'>has_tsc</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Time Stamp Counter. The RDTSC instruction is supported, including CR4.TSD for controlling privilege.</p>
</div><h4id='method.has_msr'class="method"><codeid='has_msr.v'>pub fn <ahref='#method.has_msr'class='fnname'>has_msr</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Model Specific Registers RDMSR and WRMSR Instructions. The RDMSR and WRMSR instructions are supported. Some of the MSRs are implementation dependent.</p>
</div><h4id='method.has_pae'class="method"><codeid='has_pae.v'>pub fn <ahref='#method.has_pae'class='fnname'>has_pae</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Physical Address Extension. Physical addresses greater than 32 bits are supported: extended page table entry formats, an extra level in the page translation tables is defined, 2-MByte pages are supported instead of 4 Mbyte pages if PAE bit is 1.</p>
</div><h4id='method.has_mce'class="method"><codeid='has_mce.v'>pub fn <ahref='#method.has_mce'class='fnname'>has_mce</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Machine Check Exception. Exception 18 is defined for Machine Checks, including CR4.MCE for controlling the feature. This feature does not define the model-specific implementations of machine-check error logging, reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor version to do model specific processing of the exception, or test for the presence of the Machine Check feature.</p>
</div><h4id='method.has_cmpxchg8b'class="method"><codeid='has_cmpxchg8b.v'>pub fn <ahref='#method.has_cmpxchg8b'class='fnname'>has_cmpxchg8b</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>CMPXCHG8B Instruction. The compare-and-exchange 8 bytes (64 bits) instruction is supported (implicitly locked and atomic).</p>
</div><h4id='method.has_apic'class="method"><codeid='has_apic.v'>pub fn <ahref='#method.has_apic'class='fnname'>has_apic</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>APIC On-Chip. The processor contains an Advanced Programmable Interrupt Controller (APIC), responding to memory mapped commands in the physical address range FFFE0000H to FFFE0FFFH (by default - some processors permit the APIC to be relocated).</p>
</div><h4id='method.has_sysenter_sysexit'class="method"><codeid='has_sysenter_sysexit.v'>pub fn <ahref='#method.has_sysenter_sysexit'class='fnname'>has_sysenter_sysexit</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT and associated MSRs are supported.</p>
</div><h4id='method.has_mtrr'class="method"><codeid='has_mtrr.v'>pub fn <ahref='#method.has_mtrr'class='fnname'>has_mtrr</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Memory Type Range Registers. MTRRs are supported. The MTRRcap MSR contains feature bits that describe what memory types are supported, how many variable MTRRs are supported, and whether fixed MTRRs are supported.</p>
</div><h4id='method.has_pge'class="method"><codeid='has_pge.v'>pub fn <ahref='#method.has_pge'class='fnname'>has_pge</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Page Global Bit. The global bit is supported in paging-structure entries that map a page, indicating TLB entries that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature.</p>
</div><h4id='method.has_mca'class="method"><codeid='has_mca.v'>pub fn <ahref='#method.has_mca'class='fnname'>has_mca</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Machine Check Architecture. A value of 1 indicates the Machine Check Architecture of reporting machine errors is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting MSRs are supported.</p>
</div><h4id='method.has_cmov'class="method"><codeid='has_cmov.v'>pub fn <ahref='#method.has_cmov'class='fnname'>has_cmov</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Conditional Move Instructions. The conditional move instruction CMOV is supported. In addition, if x87 FPU is present as indicated by the CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported</p>
</div><h4id='method.has_pat'class="method"><codeid='has_pat.v'>pub fn <ahref='#method.has_pat'class='fnname'>has_pat</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Page Attribute Table. Page Attribute Table is supported. This feature augments the Memory Type Range Registers (MTRRs), allowing an operating system to specify attributes of memory accessed through a linear address on a 4KB granularity.</p>
</div><h4id='method.has_pse36'class="method"><codeid='has_pse36.v'>pub fn <ahref='#method.has_pse36'class='fnname'>has_pse36</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>36-Bit Page Size Extension. 4-MByte pages addressing physical memory beyond 4 GBytes are supported with 32-bit paging. This feature indicates that upper bits of the physical address of a 4-MByte page are encoded in bits 20:13 of the page-directory entry. Such physical addresses are limited by MAXPHYADDR and may be up to 40 bits in size.</p>
</div><h4id='method.has_psn'class="method"><codeid='has_psn.v'>pub fn <ahref='#method.has_psn'class='fnname'>has_psn</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Processor Serial Number. The processor supports the 96-bit processor identification number feature and the feature is enabled.</p>
</div><h4id='method.has_ds'class="method"><codeid='has_ds.v'>pub fn <ahref='#method.has_ds'class='fnname'>has_ds</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Debug Store. The processor supports the ability to write debug information into a memory resident buffer. This feature is used by the branch trace store (BTS) and processor event-based sampling (PEBS) facilities (see Chapter 23, Introduction to Virtual-Machine Extensions, in the Intel® 64 and IA-32 Architectures Software Developers Manual, Volume 3C).</p>
</div><h4id='method.has_acpi'class="method"><codeid='has_acpi.v'>pub fn <ahref='#method.has_acpi'class='fnname'>has_acpi</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Thermal Monitor and Software Controlled Clock Facilities. The processor implements internal MSRs that allow processor temperature to be monitored and processor performance to be modulated in predefined duty cycles under software control.</p>
</div><h4id='method.has_mmx'class="method"><codeid='has_mmx.v'>pub fn <ahref='#method.has_mmx'class='fnname'>has_mmx</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Intel MMX Technology. The processor supports the Intel MMX technology.</p>
</div><h4id='method.has_fxsave_fxstor'class="method"><codeid='has_fxsave_fxstor.v'>pub fn <ahref='#method.has_fxsave_fxstor'class='fnname'>has_fxsave_fxstor</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR instructions are supported for fast save and restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an operating system to indicate that it supports the FXSAVE and FXRSTOR instructions.</p>
</div><h4id='method.has_sse'class="method"><codeid='has_sse.v'>pub fn <ahref='#method.has_sse'class='fnname'>has_sse</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>SSE. The processor supports the SSE extensions.</p>
</div><h4id='method.has_sse2'class="method"><codeid='has_sse2.v'>pub fn <ahref='#method.has_sse2'class='fnname'>has_sse2</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>SSE2. The processor supports the SSE2 extensions.</p>
</div><h4id='method.has_ss'class="method"><codeid='has_ss.v'>pub fn <ahref='#method.has_ss'class='fnname'>has_ss</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Self Snoop. The processor supports the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus.</p>
</div><h4id='method.has_htt'class="method"><codeid='has_htt.v'>pub fn <ahref='#method.has_htt'class='fnname'>has_htt</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Max APIC IDs reserved field is Valid. A value of 0 for HTT indicates there is only a single logical processor in the package and software should assume only a single APIC ID is reserved. A value of 1 for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of addressable IDs for logical processors in this package) is valid for the package.</p>
</div><h4id='method.has_tm'class="method"><codeid='has_tm.v'>pub fn <ahref='#method.has_tm'class='fnname'>has_tm</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Thermal Monitor. The processor implements the thermal monitor automatic thermal control circuitry (TCC).</p>
</div><h4id='method.has_pbe'class="method"><codeid='has_pbe.v'>pub fn <ahref='#method.has_pbe'class='fnname'>has_pbe</a>(&self) -> bool</code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#109-111'title='goto source code'>[src]</a></h4><divclass='docblock'><p>Pending Break Enable. The processor supports the use of the FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is asserted) to signal the processor that an interrupt is pending and that the processor should return to normal operation to handle the interrupt. Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.</p>
</div></div><h2id='implementations'class='small-section-header'>Trait Implementations<ahref='#implementations'class='anchor'></a></h2><divid='implementations-list'><h3id='impl-Debug'class='impl'><codeclass='in-band'>impl <aclass="trait"href="https://doc.rust-lang.org/nightly/core/fmt/trait.Debug.html"title="trait core::fmt::Debug">Debug</a> for <aclass="struct"href="../raw_cpuid/struct.FeatureInfo.html"title="struct raw_cpuid::FeatureInfo">FeatureInfo</a></code><ahref='#impl-Debug'class='anchor'></a><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#1267'title='goto source code'>[src]</a></h3><divclass='impl-items'><h4id='method.fmt'class="method hidden"><codeid='fmt.v'>fn <ahref='https://doc.rust-lang.org/nightly/core/fmt/trait.Debug.html#tymethod.fmt'class='fnname'>fmt</a>(&self, f: &mut <aclass="struct"href="https://doc.rust-lang.org/nightly/core/fmt/struct.Formatter.html"title="struct core::fmt::Formatter">Formatter</a>) -><aclass="type"href="https://doc.rust-lang.org/nightly/core/fmt/type.Result.html"title="type core::fmt::Result">Result</a></code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#1267'title='goto source code'>[src]</a></h4><divclass='docblock hidden'><p>Formats the value using the given formatter. <ahref="https://doc.rust-lang.org/nightly/core/fmt/trait.Debug.html#tymethod.fmt">Read more</a></p>
</div></div><h3id='impl-Default'class='impl'><codeclass='in-band'>impl <aclass="trait"href="https://doc.rust-lang.org/nightly/core/default/trait.Default.html"title="trait core::default::Default">Default</a> for <aclass="struct"href="../raw_cpuid/struct.FeatureInfo.html"title="struct raw_cpuid::FeatureInfo">FeatureInfo</a></code><ahref='#impl-Default'class='anchor'></a><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#1267'title='goto source code'>[src]</a></h3><divclass='impl-items'><h4id='method.default'class="method hidden"><codeid='default.v'>fn <ahref='https://doc.rust-lang.org/nightly/core/default/trait.Default.html#tymethod.default'class='fnname'>default</a>() -><aclass="struct"href="../raw_cpuid/struct.FeatureInfo.html"title="struct raw_cpuid::FeatureInfo">FeatureInfo</a></code><aclass='srclink'href='../src/raw_cpuid/lib.rs.html#1267'title='goto source code'>[src]</a></h4><divclass='docblock hidden'><p>Returns the "default value" for a type. <ahref="https://doc.rust-lang.org/nightly/core/default/trait.Default.html#tymethod.default">Read more</a></p>
</div></div><h3id='impl-TryFrom%3CU%3E'class='impl'><codeclass='in-band'>impl<T, U><aclass="trait"href="https://doc.rust-lang.org/nightly/core/convert/trait.TryFrom.html"title="trait core::convert::TryFrom">TryFrom</a><U> for T <spanclass="where fmt-newline">where<br> U: <aclass="trait"href="https://doc.rust-lang.org/nightly/core/convert/trait.Into.html"title="trait core::convert::Into">Into</a><T>, </span></code><ahref='#impl-TryFrom%3CU%3E'class='anchor'></a><aclass='srclink'href='https://doc.rust-lang.org/nightly/src/core/convert.rs.html#571-577'title='goto source code'>[src]</a></h3><divclass='impl-items'><h4id='associatedtype.Error'class="type"><codeid='Error.t'>type <ahref='https://doc.rust-lang.org/nightly/core/convert/trait.TryFrom.html#associatedtype.Error'class="type">Error</a> = <aclass="enum"href="https://doc.rust-lang.org/nightly/core/convert/enum.Infallible.html"title="enum core::convert::Infallible">Infallible</a></code></h4><divclass='docblock'><p>The type returned in the event of a conversion error.</p>
</div><h4id='method.try_from'class="method hidden"><codeid='try_from.v'>fn <ahref='https://doc.rust-lang.org/nightly/core/convert/trait.TryFrom.html#tymethod.try_from'class='fnname'>try_from</a>(value: U) -><aclass="enum"href="https://doc.rust-lang.org/nightly/core/result/enum.Result.html"title="enum core::result::Result">Result</a><T, <T as <aclass="trait"href="https://doc.rust-lang.org/nightly/core/convert/trait.TryFrom.html"title="trait core::convert::TryFrom">TryFrom</a><U>>::<aclass="type"href="https://doc.rust-lang.org/nightly/core/convert/trait.TryFrom.html#associatedtype.Error"title="type core::convert::TryFrom::Error">Error</a>></code><aclass='srclink'href='https://doc.rust-lang.org/nightly/src/core/convert.rs.html#574-576'title='goto source code'>[src]</a></h4><divclass='docblock hidden'><p>Performs the conversion.</p>
</div></div><h3id='impl-Into%3CU%3E'class='impl'><codeclass='in-band'>impl<T, U><aclass="trait"href="https://doc.rust-lang.org/nightly/core/convert/trait.Into.html"title="trait core::convert::Into">Into</a><U> for T <spanclass="where fmt-newline">where<br> U: <aclass="trait"href="https://doc.rust-lang.org/nightly/core/convert/trait.From.html"title="trait core::convert::From">From</a><T>, </span></code><ahref='#impl-Into%3CU%3E'class='anchor'></a><aclass='srclink'href='https://doc.rust-lang.org/nightly/src/core/convert.rs.html#543-548'title='goto source code'>[src]</a></h3><divclass='impl-items'><h4id='method.into'class="method hidden"><codeid='into.v'>fn <ahref='https://doc.rust-lang.org/nightly/core/convert/trait.Into.html#tymethod.into'class='fnname'>into</a>(self) -> U</code><aclass='srclink'href='https://doc.rust-lang.org/nightly/src/core/convert.rs.html#545-547'title='goto source code'>[src]</a></h4><divclass='docblock hidden'><p>Performs the conversion.</p>
</div></div><h3id='impl-TryInto%3CU%3E'class='impl'><codeclass='in-band'>impl<T, U><aclass="trait"href="https://doc.rust-lang.org/nightly/core/convert/trait.TryInto.html"title="trait core::convert::TryInto">TryInto</a><U> for T <spanclass="where fmt-newline">where<br> U: <aclass="trait"href="https://doc.rust-lang.org/nightly/core/convert/trait.TryFrom.html"title="trait core::convert::TryFrom">TryFrom</a><T>, </span></code><ahref='#impl-TryInto%3CU%3E'class='anchor'></a><aclass='srclink'href='https://doc.rust-lang.org/nightly/src/core/convert.rs.html#559-566'title='goto source code'>[src]</a></h3><divclass='impl-items'><h4id='associatedtype.Error-1'class="type"><codeid='Error.t-1'>type <ahref='https://doc.rust-lang.org/nightly/core/convert/trait.TryInto.html#associatedtype.Error'class="type">Error</a> = <U as <aclass="trait"href="https://doc.rust-lang.org/nightly/core/convert/trait.TryFrom.html"title="trait core::convert::TryFrom">TryFrom</a><T>>::<aclass="type"href="https://doc.rust-lang.org/nightly/core/convert/trait.TryFrom.html#associatedtype.Error"title="type core::convert::TryFrom::Error">Error</a></code></h4><divclass='docblock'><p>The type returned in the event of a conversion error.</p>
</div><h4id='method.try_into'class="method hidden"><codeid='try_into.v'>fn <ahref='https://doc.rust-lang.org/nightly/core/convert/trait.TryInto.html#tymethod.try_into'class='fnname'>try_into</a>(self) -><aclass="enum"href="https://doc.rust-lang.org/nightly/core/result/enum.Result.html"title="enum core::result::Result">Result</a><U, <U as <aclass="trait"href="https://doc.rust-lang.org/nightly/core/convert/trait.TryFrom.html"title="trait core::convert::TryFrom">TryFrom</a><T>>::<aclass="type"href="https://doc.rust-lang.org/nightly/core/convert/trait.TryFrom.html#associatedtype.Error"title="type core::convert::TryFrom::Error">Error</a>></code><aclass='srclink'href='https://doc.rust-lang.org/nightly/src/core/convert.rs.html#563-565'title='goto source code'>[src]</a></h4><divclass='docblock hidden'><p>Performs the conversion.</p>
</div></div><h3id='impl-Borrow%3CT%3E'class='impl'><codeclass='in-band'>impl<T><aclass="trait"href="https://doc.rust-lang.org/nightly/core/borrow/trait.Borrow.html"title="trait core::borrow::Borrow">Borrow</a><T> for T <spanclass="where fmt-newline">where<br> T: ?<aclass="trait"href="https://doc.rust-lang.org/nightly/core/marker/trait.Sized.html"title="trait core::marker::Sized">Sized</a>, </span></code><ahref='#impl-Borrow%3CT%3E'class='anchor'></a><aclass='srclink'href='https://doc.rust-lang.org/nightly/src/core/borrow.rs.html#213-215'title='goto source code'>[src]</a></h3><divclass='impl-items'><h4id='method.borrow'class="method hidden"><codeid='borrow.v'>fn <ahref='https://doc.rust-lang.org/nightly/core/borrow/trait.Borrow.html#tymethod.borrow'class='fnname'>borrow</a>(&self) ->&T</code><aclass='srclink'href='https://doc.rust-lang.org/nightly/src/core/borrow.rs.html#214'title='goto source code'>[src]</a></h4><divclass='docblock hidden'><p>Immutably borrows from an owned value. <ahref="https://doc.rust-lang.org/nightly/core/borrow/trait.Borrow.html#tymethod.borrow">Read more</a></p>
</div></div><h3id='impl-BorrowMut%3CT%3E'class='impl'><codeclass='in-band'>impl<T><aclass="trait"href="https://doc.rust-lang.org/nightly/core/borrow/trait.BorrowMut.html"title="trait core::borrow::BorrowMut">BorrowMut</a><T> for T <spanclass="where fmt-newline">where<br> T: ?<aclass="trait"href="https://doc.rust-lang.org/nightly/core/marker/trait.Sized.html"title="trait core::marker::Sized">Sized</a>, </span></code><ahref='#impl-BorrowMut%3CT%3E'class='anchor'></a><aclass='srclink'href='https://doc.rust-lang.org/nightly/src/core/borrow.rs.html#218-220'title='goto source code'>[src]</a></h3><divclass='impl-items'><h4id='method.borrow_mut'class="method hidden"><codeid='borrow_mut.v'>fn <ahref='https://doc.rust-lang.org/nightly/core/borrow/trait.BorrowMut.html#tymethod.borrow_mut'class='fnname'>borrow_mut</a>(&mut self) ->&mut T</code><aclass='srclink'href='https://doc.rust-lang.org/nightly/src/core/borrow.rs.html#219'title='goto source code'>[src]</a></h4><divclass='docblock hidden'><p>Mutably borrows from an owned value. <ahref="https://doc.rust-lang.org/nightly/core/borrow/trait.BorrowMut.html#tymethod.borrow_mut">Read more</a></p>
</div></div><h3id='impl-Any'class='impl'><codeclass='in-band'>impl<T><aclass="trait"href="https://doc.rust-lang.org/nightly/core/any/trait.Any.html"title="trait core::any::Any">Any</a> for T <spanclass="where fmt-newline">where<br> T: 'static + ?<aclass="trait"href="https://doc.rust-lang.org/nightly/core/marker/trait.Sized.html"title="trait core::marker::Sized">Sized</a>, </span></code><ahref='#impl-Any'class='anchor'></a><aclass='srclink'href='https://doc.rust-lang.org/nightly/src/core/any.rs.html#100-102'title='goto source code'>[src]</a></h3><divclass='impl-items'><h4id='method.type_id'class="method hidden"><codeid='type_id.v'>fn <ahref='https://doc.rust-lang.org/nightly/core/any/trait.Any.html#tymethod.type_id'class='fnname'>type_id</a>(&self) -><aclass="struct"href="https://doc.rust-lang.org/nightly/core/any/struct.TypeId.html"title="struct core::any::TypeId">TypeId</a></code><aclass='srclink'href='https://doc.rust-lang.org/nightly/src/core/any.rs.html#101'title='goto source code'>[src]</a></h4><divclass='docblock hidden'><p>Gets the <code>TypeId</code> of <code>self</code>. <ahref="https://doc.rust-lang.org/nightly/core/any/trait.Any.html#tymethod.type_id">Read more</a></p>
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