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https://github.com/fluencelabs/musl
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92637bb0d8
other archs use asm for the thread pointer load, so making that asm volatile is sufficient to inform the compiler that it has a "side effect" (crashing or giving the wrong result if the thread pointer was not yet initialized) that prevents reordering. however, powerpc and or1k have dedicated general purpose registers for the thread pointer and did not need to use any asm to access it; instead, "local register variables with a specified register" were used. however, there is no specification for ordering constraints on this type of usage, and presumably use of the thread pointer could be reordered across its initialization. to impose an ordering, I have added empty volatile asm blocks that produce the "local register variable with a specified register" as an output constraint.
24 lines
631 B
C
24 lines
631 B
C
static inline struct pthread *__pthread_self()
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{
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#ifdef __clang__
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char *tp;
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__asm__ __volatile__ ("mr %0, 2" : "=r"(tp) : : );
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#else
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register char *tp __asm__("r2");
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__asm__ __volatile__ ("" : "=r" (tp) );
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#endif
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return (pthread_t)(tp - 0x7000 - sizeof(struct pthread));
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}
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#define TLS_ABOVE_TP
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#define TP_ADJ(p) ((char *)(p) + sizeof(struct pthread) + 0x7000)
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#define DTP_OFFSET 0x8000
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// offset of the PC register in mcontext_t, divided by the system wordsize
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// the kernel calls the ip "nip", it's the first saved value after the 32
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// GPRs.
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#define CANCEL_REG_IP 32
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#define CANARY canary_at_end
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