mirror of
https://github.com/fluencelabs/musl
synced 2025-05-30 16:11:40 +00:00
74483c5955
this builds on commits a603a75a72bb469c6be4963ed1b55fabe675fe15 and 0ba35d69c0e77b225ec640d2bd112ff6d9d3b2af to ensure that a compiler cannot conclude that it's valid to reorder the asm to a point before the thread pointer is set up, or to treat the inline function as if it were declared with attribute((const)). other archs already use volatile asm for thread pointer loading.
31 lines
723 B
C
31 lines
723 B
C
#if ((__ARM_ARCH_6K__ || __ARM_ARCH_6ZK__) && !__thumb__) \
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|| __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
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static inline pthread_t __pthread_self()
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{
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char *p;
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__asm__ __volatile__ ( "mrc p15,0,%0,c13,c0,3" : "=r"(p) );
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return (void *)(p+8-sizeof(struct pthread));
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}
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#else
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static inline pthread_t __pthread_self()
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{
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#ifdef __clang__
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char *p;
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__asm__ __volatile__ ( "bl __a_gettp\n\tmov %0,r0" : "=r"(p) : : "cc", "r0", "lr" );
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#else
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register char *p __asm__("r0");
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__asm__ __volatile__ ( "bl __a_gettp" : "=r"(p) : : "cc", "lr" );
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#endif
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return (void *)(p+8-sizeof(struct pthread));
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}
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#endif
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#define TLS_ABOVE_TP
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#define TP_ADJ(p) ((char *)(p) + sizeof(struct pthread) - 8)
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#define CANCEL_REG_IP 18
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